Introduction to CMOS VLSI Design

Last semester given: 2019-20 Fall

Next semester to be given: 2021-22 Spring

Textbook: Weste and Harris “Integrated Circuit Design (4th Edition)”(2010)

Software tool: Cadence v.6.1 running on CentOS Linux with Europractice licence.

In the Fall 2015,  the students designed a 64-input OR/NOR gate using a cell library, starting from schematic entry and simulation for the purpose of obtaining a fast gate. They generated a layout of their gate and perform a post-layout simulation. The image below shows one corner of the design of one of the students.

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As their second project, using the same cell library the students designed an 8-bit adder to be as fast as possible. They simulated the adder after schematic entry and perform a post-layout simulation after the layout. First, they used the conventional method: Schematic entry and layout. They also learned how to generate the design using the RTL compiler automatically. The image below shows a small portion of a typical layout.

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In the Fall 2019, the students designed a 64-bit programmable digital correlator. They first developed VHDL description of the correlator, and tested its functionality using Incisive tool of Cadence. The figure below shows the timing of the design for one of the students.

IncisiveSimulation

Then the students synthesized a gate-level Verilog description using Genus tool of Cadence. They performed a placement and routing using Innovus tool of Cadence. They resynthesized the logic to include scan flip-flops for testability. They used Modus tool of Cadence to generate test patterns to test the chip after fabrication. They also used Tempus and Voltus tools of Cadence to perform accurate timing and power simulations. The final result was a GDS2 file of the chip including the bonding pads ready to be sent for fabrication. The picture below show one of the layouts generated by one student.

DigitalCorrelatorGDSII

Subjects covered:

  1. CMOS Logic, Fabrication and Layout
  2. CMOS Device Physics and Models
  3. DC and transient response
  4. Delay models
  5. Logical effort
  6. Dynamic and static power
  7. Interconnects
  8. Combinational circuits
  9. Sequential circuits
  10. Adders
  11. Comparators, counters, and others
  12. Multipliers
  13. Memories,
  14. Design for testability